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Универсальный макет для разработки цифровых фильтров с использованием цифровых процессоров

  • 77 страниц
  • 22 источника
  • Добавлена 02.02.2010
3 500 руб. 7 000 руб.
  • Содержание
  • Часть работы
  • Список литературы

Содержание

Введение
1. Литература и обзор работ, связанных с проектом
1.1. Обзор литературы
1.1.1. Зотов, В.Ю. Проектирование цифровых устройств на основе ПЛИС фирмы Xilinx в САПР WebPACK ISE
1.1.2. www.banapart.ru
1.1.2. www.fpga-clpd.ru
1.1.2. www.opencores.org
1.2. Обзор работ
1.2.3. Повышение эффективности реализации аналоговых радиотехнических устройств на базе ПЛИС
1.3. Выводы по разделу
2. Теоретическая часть
2.1. Использование ПЛИС в современной цифровой схемотехнике
2.2. Основные типы ПЛИС
2.3. Достоинства и недостатки ПЛИС
2.4. Сравнение основных производителей ПЛИС
2.5. Сравнение основных САПР для проектирования цифровых устройств на основе ПЛИС фирмы Xilink
2.6. Описание САПР XilinkISE
2.7. Методы проектирования в САПР XilinkISE
2.8. Выводы по разделу
3. Расчётно-конструкторская часть
3.1. Обоснование выбора конкретного типа ПЛИС, производителя и САПР
3.2. Разработка структурной схемы стенда
3.3. Разработка структурной схемы цифрового фильтра
3.4. Разработка функциональной схемы и выбор элементов
В качестве ЦАП выбираем MAX5852: 8-разрядный, двухканальный ЦАП с токовым выходом и скоростью обновления 165Msps.
3.5. Проектирование макета
3.6. Разработка алгоритма и программы для ПК
3.7. Выводы по разделу
4. Технологическая часть
4.1. Конструкторский расчёт печатного узла фильтра
4.1.1. Выбор и обоснование типа печатной платы
4.1.2. Выбор и обоснование технологии изготовления ПП
4.1.3. Выбор и обоснование класса точности
4.1.4. Выбор габаритных размеров и конфигурации ПП
4.1.5. Выбор материала основания ПП
4.1.6. Расчет параметров проводящего рисунка с учетом технологических погрешностей его получения
4.1.7. Расчет диаметров отверстий и контактных площадок
4.1.8. Расчет минимальной ширины проводников
4.1.9. Расчет минимальных зазоров между элементами
4.2. Выводы по разделу
5. Заключение
6. Список использованных источников
Приложение А. Исходные тексты программы.

Фрагмент для ознакомления

numeric_std.all;
use ieee.std_logic_arith.all;

entity CoefficientTest is
end entity CoefficientTest;

architecture test of CoefficientTest is

type SineArray is array (integer range 0 to 38) of unsigned (7 downto 0);
signal Sine : unsigned(7 downto 0) := (others => '0');
signal Data, NewData : SineArray;
signal SineToFIR : std_logic_vector(7 downto 0);

component FinalBalancedFIR IS
PORT (
Load : IN std_logic;
Ct0 : OUT std_logic;
Ct1 : OUT std_logic;
nRST : IN std_logic;
Ct2 : OUT std_logic;
Ct3 : OUT std_logic;
Total10 : OUT std_logic;
Total11 : OUT std_logic;
Total12 : OUT std_logic;
Total13 : OUT std_logic;
Total14 : OUT std_logic;
Total15 : OUT std_logic;
Qco0 : OUT std_logic;
Qco1 : OUT std_logic;
Qco2 : OUT std_logic;
Qco3 : OUT std_logic;
Qco4 : OUT std_logic;
Qco5 : OUT std_logic;
Qco6 : OUT std_logic;
Qco7 : OUT std_logic;
Dsg0 : IN std_logic;
Dsg1 : IN std_logic;
Dsg2 : IN std_logic;
Dsg3 : IN std_logic;
Dsg4 : IN std_logic;
Dsg5 : IN std_logic;
Dsg6 : IN std_logic;
Dsg7 : IN std_logic;
Total0 : OUT std_logic;
Total1 : OUT std_logic;
Total2 : OUT std_logic;
Total3 : OUT std_logic;
Total4 : OUT std_logic;
Total5 : OUT std_logic;
Total6 : OUT std_logic;
Total7 : OUT std_logic;
Total8 : OUT std_logic;
Total9 : OUT std_logic;
Clk : IN std_logic;
nCt0 : OUT std_logic;
nCt1 : OUT std_logic;
nCt2 : OUT std_logic;
nCt3 : OUT std_logic;
Qsg0 : OUT std_logic;
Qsg1 : OUT std_logic;
Qsg2 : OUT std_logic;
Qsg3 : OUT std_logic;
Qsg4 : OUT std_logic;
Qsg5 : OUT std_logic;
Qsg6 : OUT std_logic;
Qsg7 : OUT std_logic;
Dco0 : IN std_logic;
Dco1 : IN std_logic;
Dco2 : IN std_logic;
Dco3 : IN std_logic;
Dco4 : IN std_logic;
Dco5 : IN std_logic;
Dco6 : IN std_logic;
Dco7 : IN std_logic
);
END component;

signal Ct_tb, nCt_tb : std_logic_vector(3 downto 0);
signal SigOut_tb, Dco_tb, Coeff_tb : std_logic_vector(7 downto 0);
signal Clk_tb, nRST_tb : std_logic := '0';
signal Load_tb : std_logic;
signal Total_tb : std_logic_vector(15 downto 0);

begin

-- input signal
NewData(0) <= CONV_UNSIGNED(0,8);
NewData(1) <= CONV_UNSIGNED(0,8);
NewData(2) <= CONV_UNSIGNED(0,8);
NewData(3) <= CONV_UNSIGNED(0,8);
NewData(4) <= CONV_UNSIGNED(0,8);
NewData(5) <= CONV_UNSIGNED(0,8);
NewData(6) <= CONV_UNSIGNED(0,8);
NewData(7) <= CONV_UNSIGNED(0,8);
NewData(8) <= CONV_UNSIGNED(0,8);
NewData(9) <= CONV_UNSIGNED(0,8);
NewData(10) <= CONV_UNSIGNED(0,8);
NewData(11) <= CONV_UNSIGNED(0,8);
NewData(12) <= CONV_UNSIGNED(0,8);
NewData(13) <= CONV_UNSIGNED(0,8);
NewData(14) <= CONV_UNSIGNED(0,8);
NewData(15) <= CONV_UNSIGNED(0,8);
NewData(16) <= CONV_UNSIGNED(0,8);
NewData(17) <= CONV_UNSIGNED(0,8);
NewData(18) <= CONV_UNSIGNED(0,8);
NewData(19) <= CONV_UNSIGNED(0,8);
NewData(20) <= CONV_UNSIGNED(0,8);
NewData(21) <= CONV_UNSIGNED(0,8);
NewData(22) <= CONV_UNSIGNED(0,8);
NewData(23) <= CONV_UNSIGNED(0,8);
NewData(24) <= CONV_UNSIGNED(0,8);
NewData(25) <= CONV_UNSIGNED(0,8);
NewData(26) <= CONV_UNSIGNED(1,8);
NewData(27) <= CONV_UNSIGNED(0,8);
NewData(28) <= CONV_UNSIGNED(0,8);

process is
begin

for i in 0 to 28 loop
if(i = 0) then
Sine <= "00000000";
else
--Sine <= Data(i);
Sine <= NewData(i);
end if;
wait for 250 us;
end loop;
end process;

SineToFIR <= std_logic_vector(Sine);

FIR : FinalBalancedFIR
PORT MAP(
Load => Load_tb,
Ct0 => Ct_tb(0),
Ct1 => Ct_tb(1),
nRST => nRST_tb,
Ct2 => Ct_tb(2),
Ct3 => Ct_tb(3),
Total10 => Total_tb(10),
Total11 => Total_tb(11),
Total12 => Total_tb(12),
Total13 => Total_tb(13),
Total14 => Total_tb(14),
Total15 => Total_tb(15),
Qco0 => Coeff_tb(0),
Qco1 => Coeff_tb(1),
Qco2 => Coeff_tb(2),
Qco3 => Coeff_tb(3),
Qco4 => Coeff_tb(4),
Qco5 => Coeff_tb(5),
Qco6 => Coeff_tb(6),
Qco7 => Coeff_tb(7),
Dsg0 => SineToFIR(0),
Dsg1 => SineToFIR(1),
Dsg2 => SineToFIR(2),
Dsg3 => SineToFIR(3),
Dsg4 => SineToFIR(4),
Dsg5 => SineToFIR(5),
Dsg6 => SineToFIR(6),
Dsg7 => SineToFIR(7),
Total0 => Total_tb(0),
Total1 => Total_tb(1),
Total2 => Total_tb(2),
Total3 => Total_tb(3),
Total4 => Total_tb(4),
Total5 => Total_tb(5),
Total6 => Total_tb(6),
Total7 => Total_tb(7),
Total8 => Total_tb(8),
Total9 => Total_tb(9),
Clk => Clk_tb,
nCt0 => nCt_tb(0),
nCt1 => nCt_tb(1),
nCt2 => nCt_tb(2),
nCt3 => nCt_tb(3),
Qsg0 => SigOut_tb(0),
Qsg1 => SigOut_tb(1),
Qsg2 => SigOut_tb(2),
Qsg3 => SigOut_tb(3),
Qsg4 => SigOut_tb(4),
Qsg5 => SigOut_tb(5),
Qsg6 => SigOut_tb(6),
Qsg7 => SigOut_tb(7),
Dco0 => Dco_tb(0),
Dco1 => Dco_tb(1),
Dco2 => Dco_tb(2),
Dco3 => Dco_tb(3),
Dco4 => Dco_tb(4),
Dco5 => Dco_tb(5),
Dco6 => Dco_tb(6),
Dco7 => Dco_tb(7)
);

nRST_tb <= '1' after 210 ns;
Clk_tb <= not Clk_tb after 125 us;
Load_tb <= '0', '1' after 310 ns, '0' after 410 ns, -- one load
'1' after 510 ns, '0' after 610 ns,
'1' after 710 ns, '0' after 810 ns, -- three loads
'1' after 910 ns, '0' after 1010 ns,
'1' after 1110 ns, '0' after 1210 ns, -- five loads
'1' after 1310 ns, '0' after 1410 ns,
'1' after 1510 ns, '0' after 1610 ns, -- seven loads
'1' after 1710 ns, '0' after 1810 ns,
'1' after 1910 ns, '0' after 2010 ns, -- nine loads
'1' after 2110 ns, '0' after 2210 ns,
'1' after 2310 ns, '0' after 2410 ns, -- eleven loads
'1' after 2510 ns, '0' after 2610 ns,
'1' after 2710 ns, '0' after 2810 ns, -- thirteen loads
'1' after 2910 ns, '0' after 3010 ns,
'1' after 3110 ns, '0' after 3210 ns; -- fifteen loads
-- PROPER COEFFICIENTS
Dco_tb(7 downto 0) <= "10000110", "00000000" after 500 ns, "00001000" after 700 ns, "00000000" after 900 ns,
"10001110" after 1100 ns, "00000000" after 1300 ns, "00101001" after 1500 ns, "01000000" after 1700 ns, "00101001" after 1900 ns,
"00000000" after 2100 ns, "10001110" after 2300 ns, "00000000" after 2500 ns, "00001000" after 2700 ns,
"00000000" after 2900 ns, "10000110" after 3100 ns;



end architecture;


LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Comb0 IS PORT (
nQ1 : IN std_logic;
nQ2 : IN std_logic;
nQ3 : IN std_logic;
D0 : OUT std_logic;
Q1 : IN std_logic;
Q2 : IN std_logic;
Q3 : IN std_logic
);

END Comb0;



ARCHITECTURE STRUCTURE OF Comb0 IS

-- COMPONENTS

COMPONENT \7432\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

COMPONENT \7408\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL N00568 : std_logic;
SIGNAL N00529 : std_logic;
SIGNAL N00952 : std_logic;
SIGNAL N00835 : std_logic;
SIGNAL N01003 : std_logic;
SIGNAL N01058 : std_logic;
SIGNAL N00913 : std_logic;
SIGNAL N01592 : std_logic;
SIGNAL N01553 : std_logic;
SIGNAL VCC : std_logic;
SIGNAL GND : std_logic;
SIGNAL N03522 : std_logic;

-- GATE INSTANCES

BEGIN
U15 : \7432\ PORT MAP(
A_A => N00568,
B_A => N01592,
Y_A => D0,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U16 : \7432\ PORT MAP(
A_A => N00529,
B_A => N01058,
Y_A => N00568,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U17 : \7432\ PORT MAP(
A_A => N00952,
B_A => N01003,
Y_A => N00529,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U18 : \7408\ PORT MAP(
A_A => NQ3,
B_A => NQ2,
Y_A => N00835,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U19 : \7408\ PORT MAP(
A_A => N00835,
B_A => NQ1,
Y_A => N00952,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U20 : \7408\ PORT MAP(
A_A => NQ3,
B_A => Q2,
Y_A => N03522,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U21 : \7408\ PORT MAP(
A_A => N03522,
B_A => Q1,
Y_A => N01003,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U22 : \7408\ PORT MAP(
A_A => Q3,
B_A => Q2,
Y_A => N00913,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U23 : \7408\ PORT MAP(
A_A => N00913,
B_A => NQ1,
Y_A => N01058,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U24 : \7408\ PORT MAP(
A_A => Q3,
B_A => NQ2,
Y_A => N01553,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U25 : \7408\ PORT MAP(
A_A => N01553,
B_A => Q1,
Y_A => N01592,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
END STRUCTURE;



LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Comb1 IS PORT (
nQ0 : IN std_logic;
nQ2 : IN std_logic;
nQ3 : IN std_logic;
D1 : OUT std_logic;
Q0 : IN std_logic;
Q1 : IN std_logic;
Q2 : IN std_logic;
Q3 : IN std_logic
);

END Comb1;



ARCHITECTURE STRUCTURE OF Comb1 IS

-- COMPONENTS

COMPONENT \7432\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

COMPONENT \7408\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL N01073 : std_logic;
SIGNAL N00571 : std_logic;
SIGNAL N00331 : std_logic;
SIGNAL N00370 : std_logic;
SIGNAL N00499 : std_logic;
SIGNAL N00448 : std_logic;
SIGNAL N00409 : std_logic;
SIGNAL VCC : std_logic;
SIGNAL GND : std_logic;
SIGNAL N00775 : std_logic;

-- GATE INSTANCES

BEGIN
U1 : \7432\ PORT MAP(
A_A => N00775,
B_A => N00571,
Y_A => N00331,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U2 : \7432\ PORT MAP(
A_A => N00331,
B_A => N00499,
Y_A => N00370,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U3 : \7432\ PORT MAP(
A_A => N00370,
B_A => N00448,
Y_A => D1,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U5 : \7408\ PORT MAP(
A_A => Q1,
B_A => NQ0,
Y_A => N00775,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U6 : \7408\ PORT MAP(
A_A => Q3,
B_A => Q2,
Y_A => N01073,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U7 : \7408\ PORT MAP(
A_A => N01073,
B_A => Q1,
Y_A => N00499,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U8 : \7408\ PORT MAP(
A_A => NQ3,
B_A => NQ2,
Y_A => N00409,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U9 : \7408\ PORT MAP(
A_A => N00409,
B_A => Q0,
Y_A => N00448,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U10 : \7408\ PORT MAP(
A_A => N01073,
B_A => Q0,
Y_A => N00571,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
END STRUCTURE;


LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Comb2 IS PORT (
nQ0 : IN std_logic;
nQ1 : IN std_logic;
nQ3 : IN std_logic;
D2 : OUT std_logic;
Q0 : IN std_logic;
Q1 : IN std_logic;
Q2 : IN std_logic
);

END Comb2;



ARCHITECTURE STRUCTURE OF Comb2 IS

-- COMPONENTS

COMPONENT \7408\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

COMPONENT \7432\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL VCC : std_logic;
SIGNAL GND : std_logic;
SIGNAL N00390 : std_logic;
SIGNAL N00429 : std_logic;
SIGNAL N00468 : std_logic;
SIGNAL N00507 : std_logic;
SIGNAL N00546 : std_logic;
SIGNAL N00592 : std_logic;
SIGNAL N00638 : std_logic;
SIGNAL N00684 : std_logic;

-- GATE INSTANCES

BEGIN
U1 : \7408\ PORT MAP(
A_A => Q2,
B_A => NQ1,
Y_A => N00684,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U2 : \7408\ PORT MAP(
A_A => Q2,
B_A => Q0,
Y_A => N00638,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U3 : \7408\ PORT MAP(
A_A => NQ3,
B_A => Q1,
Y_A => N00468,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U4 : \7408\ PORT MAP(
A_A => N00468,
B_A => NQ0,
Y_A => N00592,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U5 : \7408\ PORT MAP(
A_A => NQ3,
B_A => Q2,
Y_A => N00507,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U6 : \7408\ PORT MAP(
A_A => N00507,
B_A => Q1,
Y_A => N00546,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U7 : \7432\ PORT MAP(
A_A => N00684,
B_A => N00638,
Y_A => N00390,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U8 : \7432\ PORT MAP(
A_A => N00390,
B_A => N00592,
Y_A => N00429,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U9 : \7432\ PORT MAP(
A_A => N00429,
B_A => N00546,
Y_A => D2,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
END STRUCTURE;


LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Comb3 IS PORT (
nQ0 : IN std_logic;
nQ1 : IN std_logic;
D3 : OUT std_logic;
Q0 : IN std_logic;
Q1 : IN std_logic;
Q2 : IN std_logic;
Q3 : IN std_logic
);

END Comb3;



ARCHITECTURE STRUCTURE OF Comb3 IS

-- COMPONENTS

COMPONENT \7432\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

COMPONENT \7408\
PORT (
A_A : IN std_logic;
B_A : IN std_logic;
Y_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
A_B : IN std_logic;
B_B : IN std_logic;
Y_B : OUT std_logic;
A_C : IN std_logic;
B_C : IN std_logic;
Y_C : OUT std_logic;
A_D : IN std_logic;
B_D : IN std_logic;
Y_D : OUT std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL N00538 : std_logic;
SIGNAL N00756 : std_logic;
SIGNAL N00448 : std_logic;
SIGNAL N00370 : std_logic;
SIGNAL N00487 : std_logic;
SIGNAL N00331 : std_logic;
SIGNAL N00586 : std_logic;
SIGNAL N00409 : std_logic;
SIGNAL GND : std_logic;
SIGNAL VCC : std_logic;

-- GATE INSTANCES

BEGIN
U1 : \7432\ PORT MAP(
A_A => N00756,
B_A => N00586,
Y_A => N00409,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U2 : \7432\ PORT MAP(
A_A => N00409,
B_A => N00538,
Y_A => N00448,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U3 : \7432\ PORT MAP(
A_A => N00448,
B_A => N00487,
Y_A => D3,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U4 : \7408\ PORT MAP(
A_A => Q3,
B_A => Q1,
Y_A => N00756,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U5 : \7408\ PORT MAP(
A_A => Q3,
B_A => Q0,
Y_A => N00586,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U6 : \7408\ PORT MAP(
A_A => Q2,
B_A => NQ1,
Y_A => N00331,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U7 : \7408\ PORT MAP(
A_A => N00331,
B_A => NQ0,
Y_A => N00538,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U8 : \7408\ PORT MAP(
A_A => Q3,
B_A => Q2,
Y_A => N00370,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
U9 : \7408\ PORT MAP(
A_A => N00370,
B_A => Q0,
Y_A => N00487,
VCC => VCC,
GND => GND,
A_B => 'Z',
B_B => 'Z',
Y_B => OPEN,
A_C => 'Z',
B_C => 'Z',
Y_C => OPEN,
A_D => 'Z',
B_D => 'Z',
Y_D => OPEN
);
END STRUCTURE;












42

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